1. Field of the Invention
The present invention relates generally to programmable chips, and more particularly to clustering of programmable elements in field programmable integrated circuits (ICs).
2. Description of Related Art
Field programmable gate arrays (FPGAs) are often selected by designers to provide a flexible approach to the programming and re-programming of integrated circuits, in order to accommodate a system specification, correct errors in the system, or make improvements to the system by reprogramming of the field programmable gate array. One conventional field programmable gate array architecture is implemented using groups of look-up tables and programmable interconnect circuits. While the look-up tables and sequential elements are connected to each other, the connections to the groups of look-up tables typically originate from a switchbox located in each group of the look-up table. A hierarchical interconnect structure connects to elements in a look-up table through a switchbox, thereby serving as the primary source of connecting look-up tables from one logic block to another logic block. The inputs to the look-up tables are therefore generated primarily from the switch box. The look-up table outputs are directly fed to other look-up tables as well as the elements within the look-up tables, but the connections to other look-up tables' inputs are made through the switch box.
Although field programmable gate arrays enable user programming of integrated circuits, these integrated circuits typically produce slower performance (clock speed) because of the delays through the transistors, switches or multiplexers used to program the interconnects between configurable logic elements. Each logic element can be connected to a multitude of other logic elements through switches in which the path from one programmable logic element to the next may be strewn with many switches, slowing down circuit operation. Some paths in a programmable IC are not as critical as others. Therefore, a customized programmable IC can be designed such that speed in the critical paths is optimized over other non-critical paths.
Routing elements have increasingly been added to programmable logic devices/ICs so that routing elements now typically occupy a much larger area than the configurable logic elements themselves. Adding to the problem is the fact that routing delays are typically much greater than logic delays, resulting in a slow operating clock frequency. In a conventional implementation, a large fraction of the routing elements may be redundant.
As semiconductor processes advance into deep sub-micron regimes, the cost of manufacturing a complex Application-Specific Integrated-Circuit (ASIC) chip using state-of-the-art technology is sky-rocketing. As a viable solution which will reduce costs and shorten product development cycles while minimizing production risks, field programmable gate arrays have been gaining more acceptance in various applications than ever before. Traditional homogeneous field programmable gate arrays are mainly based on programmable Look-Up Tables (LUTs). The logic density and performance of traditional homogeneous filed programmable gate arrays are usually inferior to ASIC implementations.
Efforts have been mounted to improve the overall performance of field programmable gate arrays. It is desirable to have a method that improves the performance of programmable integrated circuits for use with innovative hardware solutions.